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cyncp8019 2 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-02043 rev. *b revised august 27, 2003 cyncp80192 network database coprocessor
cyncp8019 2 document #: 38-02043 rev. *b page 2 of 42 contents 1.0 overview .................................................................................................................. .................... 5 2.0 features .................................................................................................................. .................... 6 3.0 functional description .................................................................................................... ..... 7 3.1 configuration registers ................................................................................................... ........... 7 3.2 operating registers ....................................................................................................... ............. 7 3.3 pipeline and table management and bus protocol conversion logic ....................................... 7 3.4 nse interface ............................................................................................................. ................. 7 3.5 associative ssram interface ............................................................................................... ...... 7 4.0 signal description ........................................................................................................ ........... 8 5.0 clocks .................................................................................................................... ..................... 11 6.0 registers ................................................................................................................. .................. 12 6.1 coprocessor interface register ............................................................................................ .... 12 6.2 configuration and status registers ........................................................................................ .. 12 7.0 operating registers ....................................................................................................... ...... 15 7.1 address mapping ........................................................................................................... ........... 15 7.2 context descriptor organization ........................................................................................... .... 16 7.3 context descriptor commands ............................................................................................... .. 16 8.0 ndc subsystem power-up initialization procedure ................................................ 23 9.0 zbt pipelined ssram interface mode ............................................................................. 24 10.0 zbt flowthrough ssram interface mode .................................................................. 25 11.0 syncburst pipelined ssram interface (early write) ............................................ 26 12.0 syncburst pipelined ssram interface mode (late write) ................................... 27 13.0 application information .................................................................................................. .28 14.0 information on external transceivers .................................................................... 29 15.0 jtag (1149.1) testing .................................................................................................... ......... 30 16.0 electrical characteristics ............................................................................................ 31 17.0 ordering information ..................................................................................................... ... 39 18.0 package drawings ......................................................................................................... ...... 40
cyncp8019 2 document #: 38-02043 rev. *b page 3 of 42 list of figures figure 2-1. cyncp80192 block diagram ........................................................................................... .... 6 figure 5-1. ndc clocks......................................................................................................... ................ 11 figure 9-1. zbt pipelined sram interface (mode 000) ........................................................................ 24 figure 10-1. zbt flowthrough ssram interface (mode 001)............................................................... 25 figure 11-1. syncburst pipelined ssram interface (early write) ........................................................ 26 figure 12-1. syncburst pipelined ssram interface (late write).......................................................... 27 figure 13-1. configuration 1?associative ssram mode .................................................................... 28 figure 13-2. configuration 2?index mode........................................................................................ .... 28 figure 13-3. switching systems block diagram ................................................................................... .28 figure 14-1. use of transceiver enables ........................................................................................ ...... 29 figure 14-2. transceiver connected between cynpc80192 and cynse70xxx devices ................. 29 figure 16-1. pinout diagram.................................................................................................... .............. 33 figure 18-1. package bottom view ............................................................................................... ........ 40 figure 18-2. package side view ................................................................................................. .......... 40 figure 18-3. package top view .................................................................................................. .......... 41
cyncp8019 2 document #: 38-02043 rev. *b page 4 of 42 list of tables table 4-1. search coprocessor pin description ................................................................................. .... 8 table 6-1. register partitions for coprocessor access ........................................................................ 1 2 table 6-2. configuration and status registers area ............................................................................ 12 table 6-3. configuration register ............................................................................................. ............ 12 table 6-4. error and status register .......................................................................................... .......... 13 table 6-5. error codes ........................................................................................................ ................. 13 table 6-6. information register description ................................................................................... ...... 14 table 7-1. operating registers addressing mapping (adr[9] = 1) ...................................................... 15 table 7-2. context descriptor organization .................................................................................... ..... 16 table 7-3. descriptor command ................................................................................................. ..........16 table 7-4. read command ....................................................................................................... ........... 18 table 7-5. write command ...................................................................................................... ............. 18 table 7-6. search data ........................................................................................................ ................. 18 table 7-7. move command parameters ............................................................................................ ... 19 table 7-8. swap command parameters ............................................................................................ .. 19 table 7-9. ssram data ......................................................................................................... .............. 19 table 7-10. nse data, mask, and register locations ......................................................................... 19 table 7-11. read response at result register 0 ................................................................................ 19 table 7-12. data read from nse ................................................................................................ ......... 20 table 7-13. data read from ssram .............................................................................................. ..... 20 table 7-14. write/move/swap/learn results register 0 ...................................................................... 20 table 7-15. result register 0 for search operation ............................................................................ .21 table 7-16. result register 1 (search result bit in data field = 0) ..................................................... 21 table 7-17. result register 1 (search result bit in data field = 1) ..................................................... 21 table 7-18. search response in result register 0 (type i) ................................................................. 21 table 7-19. index bits for nses ............................................................................................... ............22 table 15-1. test access port controller instructions .......................................................................... .30 table 15-2. test access port device id register ............................................................................... .30 table 16-1. electrical characteristics ........................................................................................ ........... 31 table 16-2. capacitance ....................................................................................................... ................ 31 table 16-3. operating conditions .............................................................................................. ........... 31 table 16-4. ac timing parameters for pipelined zbt ssram and syncburst ssram ..................... 31 table 16-5. ac timing parameters for zbt and flow-through ssram ............................................. 32 table 16-6. cynpc80192 pinout description ..................................................................................... .34 table 17-1. ordering information .............................................................................................. ............ 39
cyncp8019 2 document #: 38-02043 rev. *b page 5 of 42 1.0 overview cypress semiconductor corporation?s (cypress?s) network database coprocessor (ndc) performs the following three primary functions. interconnection bridge function . the cyncp80192 device acts as a bridge between network processor(s) and a search subsystem of cypress?s cynse70xxx network search engines (nses) plus optional associated ssrams that contain a search database and the associated data for a variety of network protocol layers. the cyncp80192 device interfaces to the network processor with an ssram interface and offloads the search function to provide support for fast packet processing in routers and switches. pipeline management function . cypress?s nses have a pipelined architecture to optimize search performance and through- put. the cyncp80192 device manages the pipeline for optimal search performance and packs instructions back to back in order to avoid any bubbles in the pipeline. table management function . the cyncp80192 device builds on the simple instructions of the nses to provide advanced instructions for table management. there are two ways to build the ndc system. in the first system the associative data srams are connected to the cyncp80192 device and the nse(s) (see ?ndc subsystem power-up initialization procedure? on page 23), and the cyncp80192 device returns the associated data in response to a search operation. this type of implementation is suited to applications where the associative data size is up to eight bytes. in the second system, the cyncp80192 device returns the index of the successful search entry to the network processor. the network processor uses this index to access ssrams in order to get the required results. the ssrams containing the associative data are connected directly to the network processor?s ssram bus. this is suitable for applications where the associative data size is longer than eight bytes. the ndc runs up to 100 mhz. at that speed and running with a 64-bit bus interface, the ndc performs at a peak rate of 33 millio n searches on 68-bit entries, 25 million searches on 136-bit entries, and 16.67 million searches on 272-bit entries. at 100-mhz speed and running with a 32-bit bus interface, the ndc performs at a peak rate of 25 million searches on 68-bit entries, 16.67 million searches on 136-bit entries, and 10 million searches on 272-bit entries. the ndc supports centralized, multiple layer, multiwidth tables in order to provide cost effective search solutions for etherne t, asynchronous transfer mode (atm), and sonet-based switches and routing systems. it supports the following advanced capabil- ities: quality of service (qos), class of service (cos), virtual private network (vpn), packet and flow classification, and sec urity.
cyncp8019 2 document #: 38-02043 rev. *b page 6 of 42 2.0 features ? the hardware interface to the ndc uses an ssram interface. the cyncp80192 device supports zbt ? pipelined, zbt flowthrough, and syncburst ? pipelined (late and early write) types of ssrams . all instructions and/or responses are mapped into the ssram address (adr) space . the cyncp80192 device provides simultaneous multiple layer, variable-width tables (68, 136, 272) . there is support for table sizes up to four million 34 entries . there are 33 million searches per second (msps) in the 68 configuration (cfg) . the cyncp80192 device is compatible with 1-mb, 2-mb, and 4-mb nses . it has a glueless interface to industry standard synchronous srams and nses . the cyncp80192 device uses up to 100 mhz master clock frequency . it has an ieee 1149.1 test access port . there is a 2.5v/3.3v power supply and a 388-pin bga package . the cynpc80192 ndc contains the following function blocks, shown in figure 2-1 . note: 1. 1. the device can be configured for returning sadr or sdata. network interface processor (ssram bus) configuration register operating register data return id pipeline and table management, and bus protocol conversion controller nse interface associative ssram interface sdata sadr ssrams nse [1] [1] figure 2-1. cyncp80192 block diagram
cyncp8019 2 document #: 38-02043 rev. *b page 7 of 42 3.0 functional description 3.1 configuration registers the cfg registers contain information for configuring the cynpc80192. these registers also include error, status, mask, and information registers. 3.2 operating registers this logic block contains the random access registers through which the network processor(s) perform most of the table programming, management functions, and search operations (via a request-response protocol). a network processor posts operation requests and reads responses back from this access block. 3.3 pipeline and table management and bus protocol conversion logic this unit uses pipeline management logic to optimize the search performance through the nse pipeline. this unit posts the commands to the nse and steers the results to the appropriate locations in the operating registers. it also converts the ssram interface information from a network processor into protocol cycles of the nse transactions. this unit builds on the commands provided by the nse to provide more advanced table management commands to the network processor. 3.4 nse interface this interface generates the appropriate hardware handshake with the nse(s). this block is a slave to the pipeline control unit and drives the nse(s) bus with the appropriate commands. 3.5 associative ssram interface the data transfer between the ssram and the pipeline unit takes place in this interface. the pipeline unit further transfers th is information to the operating registers.
cyncp8019 2 document #: 38-02043 rev. *b page 8 of 42 4.0 signal description table 4-1 provides information on pins and signal names for the cyncp80192 device. under the ?type? heading, i = input, o = output, and t = three-state. table 4-1. search coprocessor pin description parameter type description network processor interface irst_l i synchronous reset input . active low. initializes the device to a known state. clk [2] i coprocessor clock input . clk may be run up to 100 mhz. adr[9:0] i coprocessor location address . this 10-bit address bus adrs up to 1024 32-bit locations in the coprocessor. these 1024 locations are further divided into 512 32-bit locations of cfg area and 512 32-bit locations of the operating register area. when the data bus is configured as 64 bits wide (using the iwidth pin described below), the adr[0] is ignored by the device. when the data bus is configured as 32 bits wide (using the iwidth pin described below), all the adr bits are used by the device. data[63:0] io coprocessor data bus . only the [31:0] field of this bus is used when the coprocessor is configured for a 32-bit interface (using the iwidth pin described below). ce_l i coprocessor chip enable . this active low signal is used to enable the device. this is one of the three chip enables (ces) to the coprocessor. all three ces must be active to select the coprocessor. ce2_l i coprocessor chip enable . this active low signal is used to enable the device. this is another one of the three ces to coprocessor. all three ces must be active to select the coprocessor. ce2 i coprocessor chip enable . this active high signal is used to enable the device. this is another one of the three ces to the coprocessor. all three ces must be active to select the coprocessor. r/w_l i read/write . this input determines whether it is a read or a write cycle. a low on this pin means it is a write operation, and a high means it is a read operation. oe_l i coprocessor output enable . this active low asynchronous signal enables the output drivers of the data bus. bw_l[7:0] i synchronous byte write enables . these active low signals allow individual bytes to be written when a write cycle is active. when the data bus is configured as 32 bits wide, only bw_l[3:0] is used and the bw_l[7:4] should be tied to v dd externally. bwe_l i byte write enable . this active low signal allows the byte write signals (bw_l[7:0]) to control the write operation. strb o when the done bit is set in result register 0, strb qualifies the cpid[7:0]. the network processor can use strb signal to latch the cpid signals. cpid[7:0] o context id and processor id . when the result is ready in the descriptor, the ndc outputs the processor and context ids are concatenated as follows: {processor id, context id}. the bit length of the processor and context ids can be programmed using the cfg register 0 (see cpcfg). see the strb signal description also. intr/intr_l o this interrupt pin is asserted when the se_full, desc_afull, or error bits filed is set in the error status register. interrupt can be active high or low, depending upon the polarity selected in the cfg register. se_full o nse table full indicator to the network processor. desc_aful o this bit indicates that the descriptor array is almost full. when this flag is set, the processor can send only two more commands to the descriptor. the desc_af flag will be cleared if more that two descriptors are available. nse command and dq bus clk2x o nse master clock . cynpc80192 drives this clk to the nse. the frequency of this clk is twice the frequency of the nse. this clk runs up to 100 mhz and is derived by buffering the input clk at the coprocessor interface. phs_l o phase signal to the nse . this signal runs at half the frequency of clk2x and synchronizes the alignment of the instruction to the nse. note: 2. ?clk? is an internal clock signal.
cyncp8019 2 document #: 38-02043 rev. *b page 9 of 42 orst_l o reset output to the nse . driving orst_l low initializes the nse. cmd[8:0] o command bus to the nse . bits [1:0] specify the command and [8:2] contain the command param- eters. the descriptions of individual commands explain the details of the parameters. the encoding of commands based on the [1:0] field are: 00: read; 01: write; 10: search; 11: learn. cmdv o command valid to the nse . qualifies the cmd bus. 0: no command. 1: command valid. dq[67:0] io nse address/data bus . this signal carries the read and write address and data during register, data, and mask array operations. it carries the compare data during search operations. it also carries the ssram address during ssram accesses to the ssrams containing the associative data. dq_72 io when the cynse70128 nse is used, the four additional dq bits dq[68:71] on the cynse70128 should be connected to the dq_72 output from the cynpc80192 . the dq_72 signal is driven low from the cynpc80192. ack i read acknowledge . this signal indicates that valid data is available on the dq bus during register, data, and mask array read operations to the nse, or that the data is available on the sram data bus during read operations of the sram containing associative data. eot i end of transfer . this signal indicates the end of a burst transfer during read or write burst opera- tions to the nse. ssf i search successful flag . this signal indicates that the search was successful in the nse bank. ssv i search successful flag valid . when asserted, this signal qualifies the ssf signal. full i nse entries full indicator . xver_0 o transceiver enable for driving signals to the nse. active high . [3] xver_0_l o transceiver enable for driving signals from the nse. active low . [3] xver_1 o transceiver enable for driving signals to the nse. active high . [3] xver_1_l o transceiver enable for driving signals from the nse. active low . [3] xver_2 o transceiver enable for driving signals to the nse. active high . [3] xver_2_l o transceiver enable for driving signals from the nse. active low . [3] associated sram interface sdata[63:0]/ sadr[23:0] i/o i/o sram data/address . this bus contains either the data from the associative ssram or the adr (index) from an nse, depending on the value of the sram present bit in cfg register 0. {sdata[63:0]} from ssrams should be connected to the 64-bit bus if the associative ssram is present, or else {sadr[23:0]} from the nses should be connected to the 64-bit bus. soe_l i ssram output enable . this signal is the output enable control for the off-chip ssram bank that contains associative data and is driven by the nse. sclk o ssram clock . this is the same in phase and frequency as the one created internally by the nse. it is generated by dividing clk by two, and is used to drive the ssram clk input. configuration iwidth i this signal selects coprocessor data bus width. 1: 64 bits; 0: 32 bits. big/ltl_l i this selects how data from the network processor is interpreted. 1: big endian; 0: little endian. ifc_cfg[2:0] i this signal selects coprocessor interface type: 000: zbt pipelined mode 001: zbt flowthrough mode 010: syncburst pipelined mode (early write) 011: syncburst pipelined mode (late write) 100-111: reserved. note: 3. detailed information on the external transceiver is given in ?information on external transceivers? on page 29. table 4-1. search coprocessor pin description (continued) parameter type description
cyncp8019 2 document #: 38-02043 rev. *b page 10 of 42 test access port tdi i ieee 1149 jtag test data in . tck i ieee 1149 jtag test clock . tdo t ieee 1149 jtag test data out . tms i ieee 1149 jtag test mode select . trst_l i ieee 1149 jtag reset . table 4-1. search coprocessor pin description (continued) parameter type description
cyncp8019 2 document #: 38-02043 rev. *b page 11 of 42 5.0 clocks the cynpc80192 receives up to a 100-mhz master clk at the coprocessor interface. the cynpc80192 then generates the clk2x and a phase signal phs_l for the nses, and the sclk for the associative data ssrams, as shown in figure 5-1 . input clk to cynpc80192 input signals for nses clk for ssrams clk clk2x phs_l sclk figure 5-1. ndc clocks
cyncp8019 2 document #: 38-02043 rev. *b page 12 of 42 6.0 registers 6.1 coprocessor interface register the network processor(s) access the ndc using the coprocessor (ssram) interface. the ndc has a cfg and status registers area and an operating registers area, as shown in table 6-1 . the cfg area shown in table 6-2 is used for programming the ndc via a 64-bit cfg register. [5] 6.2 configuration and status registers 6.2.1 configuration register the 64-bit cfg register contains the following fields, as shown in table 6-3 . srst . this active high bit resets the state of the device. the reset bit will be active for 32 clk cycles and will be automatically cleared after the reset has taken effect. table size (tlsz) . this determines the nse cfg for the specific table size. [6] latency of hit signals (hlat) . this determines the data access latency of associated data ssram. [7] cpcfg . this field sets the width of the processor and context ids that will be driven on the cpid bus after the completion of the operation. the contents of the cpid bus are generated by concatenating lsbs of the processor id and the lsbs of the context id. 00: cpid[7:0] = {processor id[2:0], context id[4:0]}. 01: cpid[7:0] = {processor id[3:0], context id[3:0]}. 10: cpid[7:0] = {processor id[4:0], context id[2:0]}. 11: reserved. notes: 4. the resulting registers of the context descriptors are read-only. 5. once the ndc is configured, the network processors will use the operating registers area to configure the nses, initialize an d manage the protocol layer tables, and perform searches through such tables. 6. though the ndc does not program the nse with this information, the coprocessor uses it to determine the duration of operation s such as search and learn. (more details on this field can be found in the data sheets for cynse70xxx nses.) 7. though the ndc does not program the nse with this information, the coprocessor uses it to determine the duration of operation s such as search and read from the ssrams. (more details on this field can be found in the data sheet on cynse70xxx nses.) table 6-1. register partitions for coprocessor access address abbreviation type description 0?511 cfg and status registers r/w these registers are for configuring the ndc (read/write), reporting the error code in the status register (read-only), setting up the mask register for asserting intr (read/write), and obtaining information on the device (read-only). 512?1023 adr[9] = 1 operating registers r/w dynamic access for searches and table management happens through this area of the coprocessor address space. [4] table 6-2. configuration and status registers area address configuration and status registers area 0?1 cfg register 2?3 error, status registers (read-only) 4?5 mask registers 6?7 reserved 8?9 information registers (read-only) 10?511 reserved table 6-3. configuration register configuration register [63:0] adr 63?12 11 10 9 8 7?6 5?3 2?1 0 0?1 reserved external transceiver present search result bit in data field intr_polarity ssram present cpcfg hlat tlsz srst
cyncp8019 2 document #: 38-02043 rev. *b page 13 of 42 ssram present . this field informs the coprocessor whether the associative data ssram is connected to the nse (bit is set to 1; see figure 13-1 ) or connected to the network processor sram interface (bit is set to 0; see figure 13-2 ). intr_polarity . this bit controls the polarity of the intr/intr_l signal. when this signal is high, the intr/intr_l signal is active high. when this signal is low, the intr/intr_l signal is active low. search result bit in data field . if this bit is set to 1, the hit or miss information will be attached to the associative data field in bit 63. this bit has significance only when associative ssram is present (see result register 1 for the search command). this bit does not replace the hit bit located in result register 0. external transceiver present . if an external transceiver is used to drive several nse devices, this bit should be set to 1. 6.2.2 error and status register the error and status register is 64 bits wide. table 6-4 shows the bit positions of the error status register. the errors shown in table 6-5 will be detected by the ndc and the corresponding error bit will be set in the error and status register. once it is read, the error and status register will be cleared. error bits . the error bits field holds the type of error. in the case of multiple errors, multiple error bits may be set. the context descriptor index will contain the index where the last error occurred. when an error occurs, the error bit is set along with th e done bit in result register 0. the class and type of error (soft error [se] or hard error [he]) are indicated in the error and statu s register. when an error occurs, the intr signal is asserted and a corresponding error bit is set along with the context descriptor index to identify the erroneous command. the interrupt signal is programmable as active low or active high depending upon the system requirement. see the description of the cfg register for further detail. context descriptor index . this field identifies the context descriptor that caused the last error condition. in the case of multiple errors, this field will be overwritten. desc_afull . this bit indicates that the descriptor array is almost full. when this flag is set, the processor(s) can send only two more commands to the descriptors. the desc_af flag will be cleared if more that two descriptors are available. desc_full . this bit indicates that the descriptor array is full. when this flag is set, the processor can send no commands to the descriptor. the desc_full flag is cleared upon reading the status register. se_full . [8] this bit indicates that the table in the nse is full. se . the se bit indicates that the error is recoverable and that the command has to be reissued. he . the he bit indicates that the error is not recoverable, and that the coprocessor has to be reset and reinitialized by the sof tware before further operations are attempted. 6.2.3 mask register the mask register is 64 bits wide. the bits in this field can be used to mask the intr generated by any of the bits set in the error and status register. setting the bits in this register causes the interrupt to be masked. the default value in the mask registe r is ffffffff (lower 32 bits only). note: 8. se_full may be altered as a result of executing a learn or write command by the nse. this flag will be cleared upon reading t he status register. table 6-4. error and status register 63?32 31 30 29 28 27 26?13 12?8 7?0 reserved he se se_full desc_full desc_afull reserved context desc index error bits table 6-5. error codes error bit error description 0 invalid command (se) 1 reserved 2 reserved 3 search or learn size invalid (i.e., 11 in search size field is not allowed) (se) 4 nse access time out (he) 5 reserved 6 reserved 7 reserved
cyncp8019 2 document #: 38-02043 rev. *b page 14 of 42 6.2.4 information register the information register is 64 bits wide. table 6-6 describes the lower-order 32 bits in the information register. it uses adrs 8 and 9 of the cfg register area. table 6-6. information register description adr field range initial value description 8 revision [3:0] 0001 revision number . this is the current device revision number. numbers start at one and increment by one for each revision of the device. implementation [6:4] 001 this is the cynpc80192 implementation number. 70reserved. device id [15:8] 00000011 product code for cynpc80192. mfid [31:16] 1101_1100_ 0111_1111 manufacturer id . this field is the same as the manufacturer id used in the tap controller. 9 ? [63:32] ? reserved.
cyncp8019 2 document #: 38-02043 rev. *b page 15 of 42 7.0 operating registers there are 512 uniquely addressable 32-bit-wide registers (see table 7-1 ). these 512 registers are divided into 32 descriptors and are called context descriptors (or ?context?). each context comprises 16 registers (i.e., 32 16 = 512). each of these contexts is used for storing commands, data, and responses (returned results from nses). these 32 contexts provide a 32-deep pipeline for the network processor(s) system. the allocation of contexts between the multiple processors (or one processor running multiple processors) can be done by the network processor system. for example, a network processor system having four processing elements can assign eight contexts for each processor. 7.1 address mapping table 7-1. operating registers addressing mapping (adr[9] = 1) adr[8:0] contents 0?15 context 0 16?31 context 1 32?47 context 2 48?63 context 3 64?79 context 4 80?95 context 5 96?111 context 6 112?127 context 7 128?143 context 8 144?159 context 9 160?175 context 10 176?191 context 11 192?207 context 12 208?223 context 13 223?239 context 14 240?255 context 15 256?271 context 16 272?287 context 17 288?303 context 18 304?319 context 19 320?335 context 20 336?351 context 21 352?367 context 22 368?383 context 23 384?399 context 24 400?415 context 25 416?431 context 26 432?447 context 27 448?463 context 28 464?479 context 29 480?495 context 30 496?511 context 31
cyncp8019 2 document #: 38-02043 rev. *b page 16 of 42 7.2 context descriptor organization table 7-2 shows the organization of the context descriptor. during normal operation, the network processor writes in the context descriptor block (addresses 0?9 within the block) with the command and the appropriate data and reads the results from the context descriptor block (addresses 12?15 within the block). note . in 64-bit bus mode, the even and the next odd location are accessed in the same cycle, and adr[0] is ignored. depending on the type of command, the network processor may only need to write to selected locations of data 0?3, and may only need to read from selected locations of result register 0 or 1. note . addresses 0?9 are read/write and addresses 12?15 are read-only locations. 7.3 context descriptor commands this 64-bit word (eight bytes) describes the command to the coprocessor. the contents of each of these eight bytes and a description of each of these fields are described below in table 7-3 . context id . this field contains the context id that a network processor has assigned to this specific context. processor id . this field contains the id number of the network processor that wrote the descriptor. global mask index . this field is used only for search, write, move, and swap commands to the nse(s). this field selects one of the eight global mask register (gmr) pairs from the nse bank for search, write, move and swap commands. in the case of a 272-bit search, two pairs of gmrs are used. these two pairs include one that is specified in the command and other is a subsequent pair. for example, if the gmr pair 7 is specified, the gmr pair 0 will be used as the subsequent pair for 272-bit- wide searches. search successful register index . the search successful register (ssr) index field is used only for search and write opera- tions to the nses. up to eight search successful indexes are stored in each of the nses. this field selects one of those eight registers for the search and indirect write operations to the nses. (refer to the data sheet specifications of the cynse70xxx devices for further information.) comparand register index . this field is used only for search and learn operations. this field specifies the comparand register in each of the nses that will store the comparands (as they are searched). a subsequent learn instruction can insert the stored comparands in a table residing in the nse(s). (refer to the data sheet specifications of cynse70xxx devices for further information.) table 7-2. context descriptor organization adr context descriptor organization access 0?1 command descriptor r/w 2?3 data 0 r/w 4?5 data 1 r/w 6?7 data 2 r/w 8?9 data 3 r/w 10?11 reserved ? 12?13 result register 0 r 14?15 result register 1 r table 7-3. descriptor command bit positions field description 7 6 5 43210 63?56 reserved context id 55?48 reserved processor id 47?40 reserved search successful register index reserved global mask index 39?32 reserved ssram address prefix comparand register index 31?24 reserved direct/indirect access location search size start 23?16 layer attribute/valid bit for data 3 layer attribute/valid bit for data 2 15?8 layer attribute/valid bit for data 1 layer attribute/valid bit for data 0 7?0 command
cyncp8019 2 document #: 38-02043 rev. *b page 17 of 42 ssram address prefix . in the implementation with a ssram connected to the nse (see figure 13-1 ), these three bits are used as an ssram address prefix (sap) to generate the address of the associative ssram. (refer to the data sheet specifications of the cynse70xxx devices for further information.) start . when the command and associated parameters have been written to the command descriptor, a process running on the network processor can set this bit to initiate the operation by the cynpc80192. search size . this two-bit field is used only by search and learn instructions and describes the word size for these operations. note . learn command is not supported in the 272-bit wide table. the following describes the data that will be presented to the nse for various search sizes. 000: 68 ({data 0, layer attribute/valid bit for data 0}) 001: 136 ({data 1, layer attribute/valid bit for data 1; data 0, layer attribute/valid bit for data 0}) 010: 272 ({data 3, layer attribute/valid bit for data 3; data 2, layer attribute/valid bit for data 2; data 1, layer attribute/valid bit for data 1; data 0, layer attribute/valid bit for data 0}. note . the two-bit search size must contain 00 for non-search/learn instructions. access location . this two-bit field is used by read, write, move, and swap instructions, and indicates the region accessed in the nses or the associative data ssrams. 000: nse data array. 001: nse mask array. 010: sram connected to the nse. 011: nse internal registers. direct/indirect . this one-bit field is used by read and write instructions and controls the address generation to the nses and the associated data ssrams. when this bit is set, it specifies indirect addressing using ssrs in the nses. (refer to the specifications of cynse70xxx for further information.) layer attribute and valid bit for data 0 . this field contains the three-bit layer attribute as well as a valid bit to accompany data in the data 0, in the context descriptor. the layer attributes bits may be used for maintaining multiple search tables (of diff erent widths) in the nse(s). however, if multiple search tables are not used, these bits can be used for any purpose. layer attribute and valid bit for data 1 . this field contains a three-bit layer attribute as well as a valid bit to accompany data in the data 1, in the context descriptor. the layer attributes bits may be used for maintaining multiple search tables (of diff erent widths) in the nse(s). however, if multiple search tables are not used, these bits can be used for any purpose. layer attribute and valid bit for data 2 . this field contains the three-bit layer attribute as well as a valid bit to accompany data in the data 2, in the context descriptor. the layer attributes bits may be used for maintaining multiple search tables (of diff erent widths) in the nse(s). however, if multiple search tables are not used, these bits can be used for any purpose. layer attribute and valid bit for data 3 . this field contains the three-bit layer attribute as well as valid bit to accompany data in the data 3, in the context descriptor. the layer attributes bits may be used for maintaining multiple search tables (of diff erent widths) in the nse(s). however, if multiple search tables are not used, these bits can be used for any purpose. commands . ndc currently supports six basic commands. command bits 7 through 3 are reserved and must be programmed as 0s for the following commands: 000: read 001: write 010: search 011: learn 100: move 101: swap. 7.3.1 command description and parameters read command (00 h) . table 7-4 shows the format for the read command. the read command?s structure is rd(adr). the read command uses two 64-bit words in the context descriptor, command descriptor word, and data 0 word. the read command is issued through the command descriptor. the read access location, either data array, mask array, nse register, or external ssram is encoded in the command descriptor word. bits 15?0 of the data 0 word contain the read address. bits 23?19 of the data 0 word supply the nse id (seid).
cyncp8019 2 document #: 38-02043 rev. *b page 18 of 42 result registers 0 and 1 return the result of the read operation in two 64-bit words. write command (01 h) . table 7-5 shows the format for the write command. the write command?s structure is wr(adr, dt). the write command uses three 64-bit words in the context descriptor: command word, data 0 word and data 1 word. the write command is issued through the command descriptor. the write access location could be either the data array, mask array, nse register or associative ssram connected to the nse. bits 15?0 of the data 0 word contain the write address. bits 23?19 of the data 0 supply the seid. the data 1 word contains the data bits [67:4], while the data bits [3:0] (called layer bits for data 1) are passed in the command descriptor word. search command (02h) . the search command?s structure is se(dt0) for 68-bit word, se(dt0,dt1) for 136-bit word and se(dt0,dt1,dt2,dt3) for 272-bit word. the search command uses two, three, or five 64-bit words in the context descriptor depend ing upon the size of the search entry (68-bit, 136-bit, or 272-bit). the search size is encoded in the command word, bits [26:25]. data bits [3:0] for each 68-bit nse word are stored in the command word in layer attribute bits for data 0 through data 3. the numbe r of layer attribute bits used in the command word depends upon the search size. thus, for a 68-bit search the descriptor command bits [11:8] will be used; for a 136-bit search, bits [15:8] will be used and for a 272-bit search, bits [23:8] will be used. the indices for ssr, gmr, and comparand register are stored in the command word also. (for further explanation of these indices, refer to data sheets for the cynse70xxx nses.) successive search operations are pipelined. for a 64-bit network processor interface running at 100 mhz, the ndc can sustain 33 msps for tables configured as 68 bit in the nses. for 136-bit cfg, the performance will be 25 msps, and for 272-bit cfg, the peak performance will be 16.67 msps. for a 32-bit network processor interface, the peak performance will drop by a factor of one half compared to the performance of the 64-bit interface. 7.3.2 context descriptor data 0?data 3 for the search command these words contain the search key that will be presented to the nses. table 7-6 shows the meaningful fields for each search size that are driven on the nse bus dq from the descriptors.the data driven on the dq[3:0] for various searches is picked from the command word as follows. 68-bit search: layer attribute and valid bits for data 0. 136-bit search: layer attribute and valid bits for data 0 and data 1. 272-bit search: layer attribute and valid bits for data 0, data 1, data 2, and data 3. result registers 0 and 1 return the result of the search operation. learn command (03h) . the learn command?s structure is le(indx). the learn command will use two 64-bit words (command descriptor word and data 0) in the context descriptor. the command includes an index for a comparand register of the nse, where the data to be learnt was stored by a prior search instruction. data 0 contains the data to be written in associative sra m. learn will result in error if the learn is performed when the nse se_full is high. the error bit in the result register will in dicate the error. the learn error will be set in the error and status register. move command (04 h) . the move command?s structure is mv(addr1, addr2, len). the move command utilizes two 64-bit words in the context descriptor: command descriptor word, and data 0 word. bits 15?0 of the data 0 word will contain the source addre ss; bits 23?19 will contain the seid; bits 39?24 will contain the destination address, bits 47?43 will contain the destination seid ; and bits 56?48 will contain the move block length (see table 7-7 ). current implementation restricts the maximum move block length to 256 words (of 68-bit each) in between/within the nse(s). the minimum length for the move command is four locations. table 7-4. read command address 63?24 23?19 18?16 15?0 data 0 reserved seid reserved address pointer table 7-5. write command address 63?24 23?19 18?16 15?0 data 0 reserved seid reserved address pointer data 1 data [67: 4] table 7-6. search data search size meaningful data (64 bits each) 00 data 0 ? > dq[67:4] (cycle a and b) 01 data 0 ? > dq[67:4] (cycle a), data 1 ? > dq[67:4] (cycle b) 10 data 0 ? > dq[67:4] (cycle a), data 1 ? > dq[67:4] (cycle b) data 2 ? > dq[67:4] (cycle c), data 3 ? > dq[67:4] (cycle d) 11 reserved
cyncp8019 2 document #: 38-02043 rev. *b page 19 of 42 for move instruction, data 0 is used to pass the source address pointer and seid, destination address pointer and the seid, and the number of 68 entries to be moved move/swap length. the ndc implements the move instruction as burst read and then a burst write into the nses. swap command (05h) . the swap command?s structure is sw(addr1, addr2, len). the swap command will use two 64-bit words in the context descriptor: command word, and data 0 word. bits 15?0 of the data 0 word will contain the first address; bits 23? 19 will contain the first seid; bits 39?24 will contain the second address, bits 47?43 will contain the second seid; and bits 56?4 8 will contain the swap block length (see table 7-8 ). the maximum swap block length is 128 words (of 68-bit each) in the nse. the minimum length for swap is four locations. for swap instruction, data 0 is used to pass the first address pointer and seid, the second address pointer and seid, and the number of 68 entries to be swapped. the ndc implements the swap instruction as two burst reads and then two burst writes into the nses. note . the move and swap commands will not work across the nse boundaries if several nses are cascaded. 7.3.3 ssram read/write for ssram (connected to the nse) read or write operations, data 0 is used to pass the ssram address and seid. data 1 is used for passing the data for a write operation. table 7-9 shows the format for data 0 and data 1 for accessing the ssram. for nse read and write operations, the data 0 is used to pass address and seid. data 1 is used for passing data for write operations. this 64-bit data 1 field holds data[67:4] for the nse, while data[3:0] is held in the layer attribute and valid bit s field of the command descriptor word. the nse operation can be on the array, mask array, or the command registers. table 7-10 shows the format for data 0 and data 1 for accessing the nse data, mask, and register locations. 7.3.4 result register 0 and 1 for read operation these two registers return the result of the read operation in two 64-bit words. result register 0 contains the four least sign ificant bits of data (layer attribute/valid bits) and the status of read operation along with the processor and context id. this is sho wn in table 7-11 . table 7-7. move command parameters adr 63?57 56?48 47?43 42?40 39?24 23?19 18?16 15?0 data 0 reserved move length destination seid reserved destination address pointer source seid reserved source address pointer table 7-8. swap command parameters adr 63?7 56?48 47?43 42?40 39?24 23?19 18?16 15?0 data 0 reserved swap length second seid reserved second address pointer first seid reserved first address pointer table 7-9. ssram data adr 63?24 23?19 18?16 15?0 data 0 reserved seid reserved address[15:0] data 1 data[63:0] table 7-10. nse data, mask, and register locations adr 63?24 23?19 18?16 15?0 data 0 reserved seid reserved address[15:0] data 1 data[67:4] table 7-11. read response at result register 0 bit positions associative data ssram connected to coprocessor bus 76543210 63?56 reserved 55?48 reserved 47?40 reserved 39?32 reserved processor id[4:0] 31?24 done reserved context id [4:0]
cyncp8019 2 document #: 38-02043 rev. *b page 20 of 42 processor id[4:0] . the processor id from the command descriptor is identified here. context id[4:0] . the context id from the command descriptor is identified here. done . this field indicates that the read operation is complete. when the done bit is set, the next command can be written in the descriptor. the done bit is cleared when the result register 0 is read by the network processor. se data[3:0] . this field contains the least four significant bits (layer attribute/valid bits) read from the nse 68-bit word. (this field is valid only when reads are done from the nse.) result register 1 contains the se data[67:4] read from the nse ( table 7-12 ) or data[63:0] read from the ssram connected to the nse ( table 7-13 ). 7.3.5 result register 0 and 1 for write/move/swap/learn operations only result register 0 carries meaningful data, as is shown in table 7-14 below. done . this field indicates that the command has been processed. when the done bit is set, the next command can be written in the descriptor. the done bit is cleared when the result register 0 is read by the network processor. result register 1 is not used for write/move/swap/learn commands. 7.3.6 result register 0 and 1 for search operation (case 1) for the search operation where an ssram is connected to the nse (figure 7), the result register 0 carries search status, processor id and context id and is shown in table 7-15 . the associative data is returned in result register 1 if the search succeeded, as shown in table 7-16 . in addition, if the search result in data field bit in the cfg register is set, then bit[63] of result register 1 indicates a search success (bit[63] = 1) or search failure (bit[63] = 0). in this case bits 62?0 contain the 63-bit associative data from the ssram, as is shown in table 7-17 . 23?16 reserved 15?8 reserved 7?0 reserved se data[3:0] table 7-12. data read from nse adr 63?0 result 1 se data[67:4] table 7-13. data read from ssram adr 63?0 result 1 ssram data[63:0] table 7-14. write/move/swap/learn results register 0 bit positions associative data ssram connected to coprocessor bus 76543210 63?56 reserved 55?48 reserved 47?40 reserved 39?32 reserved reserved 31?24 done reserved reserved reserved 23?16 reserved 15?8 reserved 7?0 reserved table 7-11. read response at result register 0 (continued) bit positions associative data ssram connected to coprocessor bus
cyncp8019 2 document #: 38-02043 rev. *b page 21 of 42 processor id[4:0] . the processor id from the command descriptor is identified here. context id[4:0] . the context id from the command descriptor is identified here. hit . the hit flag indicates whether the search was successful. done . this field indicates that the command has been processed. the done bit is cleared when the result register 0 is read by the network processor. a new command can be initiated by the network processor through this descriptor after the done bit has cleared. 7.3.7 result register 0 and 1 for search operation (case 2) for the search operation where the ssram is connected to the network processor (see figure 13-1 ), the result register 0 carries the search response (see table 7-18 ) and result register 1 is unused. processor id[4:0] . the processor id set in the command descriptor is set here. context id[4:0] . the context id set in the command descriptor is set here. hit . the hit flag indicates whether the search was successful. done . this field indicates that the command has been processed. the done bit is cleared when the result register 0 is read by the network processor. a new command can be initiated by the network processor through this descriptor after the done bit has cleared. table 7-15. result register 0 for search operation bit positions se data/mask array access results 76543210 63?56 reserved 55?48 reserved 47?40 reserved 39?32 reserved processor id [4:0] 31?24 done hit reserved context id [4:0] 23?16 reserved 15?8 reserved 7?0 reserved table 7-16. result register 1 (search result bit in data field = 0) adr 63?0 result 1 associative data[63:0] table 7-17. result register 1 (search result bit in data field = 1) adr 63?0 result 1 hit associative data[62:0] table 7-18. search response in result register 0 (type i) bit positions associative data ssram connected to coprocessor bus 76543210 63?56 reserved 55?48 reserved 47?40 reserved 39?32 reserved reserved processor id[4:0] 31?24 done hit reserved context id [4:0] 23?16 index [23:16] 15?8 index [15:8] 7?0 index [7:0]
cyncp8019 2 document #: 38-02043 rev. *b page 22 of 42 index . this field contains index returned by the nses where a successful hit was found. this field is valid only if the hit bit in t he result register 0 is a 1. table 7-19 below shows the number of index bits for various nses. note . cynse70032 and cynse70064 bits 23?22 of the index will always be 00. (refer to the specifications of the cynse70xxx for the description of the index returned by the nses.) note . sap is the ssram address (sadr) prefix. these bits are passed along with the command descriptor word in the sap field. 7.3.8 functional overview of context descriptor the network processor(s) can write up to 32 contexts. there can be up to 32 operations in flight through the database copro- cessing subsystem. if 30 descriptor entries are in use, the ndc will issue the desc_aful signal to inform that command descriptor ring is almost full. the database coprocessor continually executes the commands posted in the descriptors. the commands are executed and the results written in the result registers 0 and 1 of the corresponding descriptor entries. the network processor(s) will read the results and free the descriptor entry for another command. the handshake for the command handoff from the network processor uses the start bit in the command descriptor. the network processor will load the command and the associative parameter along with the start bit in the descriptors. as the start bit in a descriptor is set, the ndc will take the command and insert it in the pipeline queue for execution. the commands in the pipeli ne queue are strictly handled in a first-in, first-out manner. note . the network processor must make sure that the start bit is set in the last access to the descriptor to complete the command. the commands from the pipeline queue are continually executed by the ndc and the results are loaded back to the command initiating descriptor?s result registers 0 and 1. the handshake for the results from the ndc back to network processor is done through any of the following mechanisms: done bit cpid bus, strb signal. in the first method, after the network processor has issued a command to the ndc, the network processor will continually poll that command descriptor entry for the done bit. once done bit is set, it signals to the network processor that the results are ready in results registers 0 and 1 for readout. reading of these registers by the network processor will clear the done bit. this descriptor entry is free and may now be used for another command. in the second method, the network processor uses the interrupt mechanism for reading the command results. after the results are ready in result registers 0 and 1 and the done bit is set, the ndc will assert pins cpid[7:0] (with the concatenated proces sor and context id information) and activate the strb signal for one clk cycle. this strb signal interrupts and the cpid identifies the context and/or processor for which the result are ready. the context within that processor can wake up and read the results (result register 0 and 1) from the appropriate descriptor. reading of these registers by the network processor will reset the d one bit. this descriptor entry is free and may now be used for another command. table 7-19. index bits for nses device sap seid index cynse70032 21:19 18:14 13:0 cynse70064 21:20 19:15 14:0 cynse70128 23:21 20:16 15:0
cyncp8019 2 document #: 38-02043 rev. *b page 23 of 42 8.0 ndc subsystem power-up initialization procedure on power-up (boot), the network processor will apply the following sequence of operations. 1. write srst and cfg information to 1 in the cfg register. 2. wait at least 32 cycles, then poll on srst. 3. write the cfg registers to each of the nses, starting with the one residing at the least significant address. 4. write the cfg registers of the last nse in the depth-cascaded system, setting the ldev and lram bits to a 1. 5. the descriptor block is now ready for use by the network processor(s) for building, managing, and/or searching the database. hardware interface timing protocols?ndc interface . the network processor interface of the ndc supports a variety of ssram interfaces. it supports both syncburst as well as zbt ssrams. ifc_cfg[2:0] pins select the interface type for the device as follows. (refer to ssram specifications and application notes from such vendors as idt and micron.) 000: zbt pipelined mode 001: zbt flowthrough mode 010: syncburst pipelined mode (early write) 011: syncburst pipelined mode (late write) 100?111: reserved.
cyncp8019 2 document #: 38-02043 rev. *b page 24 of 42 9.0 zbt pipelined ssram interface mode the adr and control signals (r/w_l, bw_l[7:0], ce_l, ce2, ce2_l) are sampled on a clk edge. for write cycles, the data is sampled two cycles later; for read cycles, the data is availa ble to the processor two cycles later. both write- and read-cyc le latency is two cycles and there is no gap required between read and write operations. every cycle is available for the network processor(s) for full utilization of the bus bandwidth. see figure 9-1 . note . bwe_l is not used in this mode and should be tied inactive. clk adr[9:0] bw_l[7:0] data[63:0] ce_l ce_2 r/w_l strb cpid[7:0] 1234567 a1 a2 a3 a4 a5 a6 d1 q2 d3 d4 q5 cpid write read write write read read figure 9-1. zbt pipelined sram interface (mode 000)
cyncp8019 2 document #: 38-02043 rev. *b page 25 of 42 10.0 zbt flowthrough ssram interface mode the adr and control signals (r/w_l, bw_l[7:0], ce_l, ce2, ce2_l) are sampled on a clk edge. for write cycles, the data is sampled one cycle later; for read cycles, the data is available to the processor one cycle later. both write- and read-cycle latency is one cycle, and there is no gap required between read and write operation. every cycle is available for the network processor(s) for full utilization of the bus bandwidth. see figure 10-1 . note . bwe_l is not used in this mode and should be tied inactive. clk adr[9:0] bw_l[7:0] data[63:0] ce_l ce_2 r/w_l strb cpid[7:0] 1234567 a1 a2 a3 a4 a5 d1 q2 d3 q4 q5 cpid write read write write read ce2_l figure 10-1. zbt flowthrough ssram interface (mode 001)
cyncp8019 2 document #: 38-02043 rev. *b page 26 of 42 11.0 syncburst pipelined ssram interface (early write) the adr and control signals (r/w_l, bw_l[7:0], ce_l, ce2, ce2_l) are sampled on a clk edge. for write cycles, the data is sampled one cycle later; for read cycles, the data is available to the processor one cycle later. both write- and read-cycle latency is one cycle, and there is no gap required between read and write operation. every cycle is available for the network processor(s) for full utilization of the bus bandwidth. see figure 11-1 . note . bwe_l is not used in this mode and should be tied inactive. clk adr[9:0] a1 a2 bw_l[7:0] data[63:0] d1 q2 d3 q4 ce_l ce_2 r/w_l strb cpid[7:0] cpid write read nop read a4 a5 a3 write figure 11-1. syncburst pipelined ssram interface (early write) 1234567 8
cyncp8019 2 document #: 38-02043 rev. *b page 27 of 42 12.0 syncburst pipelined ssram interface mode (late write) the adr and control signals (r/w_l, bw_l[7:0], ce_l, ce2, ce2_l) are sampled on a clk edge. for write cycles, the data is sampled one cycle later; for read cycles, the data is available to the processor one cycle later. both write- and read-cycle latency is one cycle, and there is no gap required between read and write operation. every cycle is available for the network processor(s) for full utilization of the bus bandwidth. see figure 12-1 . note . bwe_l is not used in this mode and should be tied inactive. clk 1234567 adr[9:0] a1 a2 b w_l[7:0] d ata[63:0] d1 q2 d3 q4 ce_l ce_2 r/w_l strb cpid[7:0] cpid write read nop read 8 write a4 a5 a3 q5 figure 12-1. syncburst pipelined ssram interface (late write)
cyncp8019 2 document #: 38-02043 rev. *b page 28 of 42 13.0 application information there are two ways to build a database coprocessing subsyste m using cynpc80192, cynse70xxx, and ssrams. in the first system the associative data ssrams are connected to the coprocessor and the nse ( figure 13-1 ) and the coprocessor returns the associated data in response to a search operation. this type of implementation is suited to applications where the associat ive data size is up to eight bytes. in the second system, the coprocessor returns the index of the successful search entry. the network processor uses the index as the page offset to access the associative data from ssram directly (see figure 13-2 ). this implementation is suited to applications where the associative data size is longer than eight bytes. single or multiple network processors with the arbitration to the sram interface can access the database coprocessing subsystem to implement a parallel packet processing system, as shown in figure 13-3 . coprocessor bank ssram bank nse figure 13-1. configuration 1?associative ssram mode coprocessor ssram bank bank nse figure 13-2. configuration 2?index mode network processors network processors coprocessors ssrams figure 13-3. switching systems block diagram
cyncp8019 2 document #: 38-02043 rev. *b page 29 of 42 14.0 information on external transceivers as more nses are added to the dq bus, the capacitive load on the bus increases, reducing the bus speed. cynse80192 gets around this by using external transceivers, and provides a glueless support to add the transceivers (phillips 74alvt16652) between a bank of nses and the cynpc80192 (see figure 14-1 ). the xver_0, xver_1, and xver_2 are electrically buffered versions of the same logical signal in the cynpc80192 device. the xver_0_l, xver_1_l, and xver_2_l are also electrically buffer ed versions of the same logical signal in the cynpc80192 device. multiple copies of these signals are provided in order to increase the ability of the signal to drive many transceiver devices of eight-bit width. figure 14-2 shows one example of the distribution of signals driving the transceivers. clk (system clock) xver_0 xver_0_l transceivers transceivers transceivers cynpc80192 xver_1 xver_1_l xver_2 xver_2_l figure 14-1. use of transceiver enables transceivers cyncp80192 nses ssram figure 14-2. transceiver connected between cynpc80192 and cynse70xxx devic-
cyncp8019 2 document #: 38-02043 rev. *b page 30 of 42 15.0 jtag (1149.1) testing the cynpc80192 supports the test access port and boundary scan architecture as specified in the ieee jtag standard 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 15-1 and table 15-2 describe the operations that the test access port controller supports and the test access port device id register. table 15-1. test access port controller instructions instruction type description sample/preload mandatory sample/preload . loads the values of signals going to and from i/o pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test . uses boundary scan values shifted in from tap to test connectivity external to the device. intest optional internal test . allows slow-speed functional testing of the device using the boundary scan register to provide the i/o values. table 15-2. test access port device id register field range initial value description revision [31:28] 0001 revision number . this is the current device revision number. numbers start from one and increment by one for each revision of the device. part number [27:12] 0000 0000 0000 0011 this is the part number for this device . mfid [11:1] 000_1101_1100 manufacturer id . this field is the same as the manufacturer id used in the tap controller. lsb 0 1 least significant bit .
cyncp8019 2 document #: 38-02043 rev. *b page 31 of 42 16.0 electrical characteristics this section describes the electrical specifications, capacitance, operating conditions, dc characteristics, and ac timing para m- eters for the ndc (see table 16-1 , table 16-2 , table 16-3 , table 16-4 , and table 16-5 ). table 16-1. electrical characteristics parameter description test conditions min. max. unit i li input leakage current 0 < v in < v ddq ?10 10 ua i lo output leakage current [9] 0 < v out < v ddq ?10 10 ua v ol output low voltage 8 ma, v ddq = 3.3v 0.4 v v oh output high voltage 4 ma, v ddq = 3.3v 2.4 v i cc _core 2.5 v supply current [10] tbd ma i cc _io 3.3 v supply current tbd ma table 16-2. capacitance parameter description max. unit c in input capacitance tbd pf [11] c out output capacitance tbd pf [12] table 16-3. operating conditions parameter description min. max. unit v ddq operating voltage for io 3.14 3.45 v v dd operating supply voltage 2.37 2.63 v v ih input high voltage [13] 2.0 v dd +0.3 v v il input low voltage [14] ?0.3 0.8 v t a ambient operating temperature 0 70 oc supply voltage tolerance ?5% +5% table 16-4. ac timing parameters for pipelined zbt ssram and syncburst ssram parameter description test conditions load (pf) cynpc80192?100 cynpc80192?83 unit min. max. min. max. t clk clk period: max frequency 100 83 mhz t ckhi clk high pulse; worst-case 40%?60% duty cycle [15] 4.0 4.8 ns t cklo clk low pulse; worst-case 40%?60% duty cycle [15] 4.0 4.8 ns t sa set-up time to clk rising edge [16] 2.5 3.0 ns t ha hold time to clk rising edge [17] 1.5 1.5 ns t ckov clock to output valid (network processor interface) 30 8.0 9.0 ns t ck2x clock to clk2x delay 3.5 4.0 ns t clkphsl clock to phs_l delay 6 7 ns t ckse clock to output valid (nse interface) 40 9 11 ns t sck clock to sclk delay 5 6 ns t cksd clock to output valid (sdata) 20 10 12 ns t ckolz clock to output in low-z 3 3 ns t ckohz clock to output in high-z 6 7 ns notes: 9. applies only for outputs in three-state. 10. average operating current at maximum frequency. transient peak currents may exceed these values. 11. f = 1 mhz, v in = 0v. 12. f = 1 mhz, v out ? 0v. 13. maximum allowable applies to overshoot only (v ddq is 3.3v supply). 14. minimum allowable applies to undershoot only. 15. 1. t clkhi and t clko duty-cycle values are based on 20?80% signal levels. 16. 2. set-up time for adr, clk enable, data, read/write, ce, and byte write enable. 17. 3. hold time for adr, clk enable, data, read/write, ce, and byte write enable.
cyncp8019 2 document #: 38-02043 rev. *b page 32 of 42 table 16-5. ac timing parameters for zbt and flow-through ssram parameter description test conditions load (pf) cynpc80192?83 unit min max t clk clk period: max frequency 50 mhz t ckhi clk high pulse; worst-case 40%?60% duty cycle 8 ns t cklo clk low pulse; worst-case 40%?60% duty cycle 8 ns t sa address setup time to clk rising edge 6 ns t ha address hold time to clk rising edge 2 ns t ckov clock to output valid (network processor interface) 30 18 ns t clk2 clock to clk2x delay 4ns t clkphsl clock to phs_l delay 7ns t ckse clock to output valid (nse interface) 40 12 ns t sck clock to sclk delay 6ns t cksd clock to output valid (sdata) 20 13 ns t ckolz clock to output in low-z 3 ns t ckohz clock to output in high-z 7 ns
cyncp8019 2 document #: 38-02043 rev. *b 33 figure 16-1. pinout diagram af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 data 2 data5 data6 data9 data 12 data 15 data 18 data 21 data 23 data 26 bw_l6 bw_l3 bw_l2 bw_l1 adr1 adr4 adr7 ce2 rw_l bwe_l data 30 data 33 data 3 6 data 39 data4 2 data4 3 1 2 strb data 1 data 3 data7 data 10 data 13 data 16 data 19 data 22 data 25 bw_l7 bw_l4 clk bw_l0 adr2 adr5 adr8 ce_l oe_l data 29 data 32 data 35 data 38 data4 1 gnd data4 4 2 3 cbid1 cpid0 data 0 data4 data8 data 11 data 14 data 17 data 20 data 24 data 27 bw_l5 xver_2 _l adr0 adr3 adr6 adr9 ce2_l data 28 data 31 data 34 data 37 data4 0 gnd data4 5 data4 7 3 4 big_lt l_l cpid2 irst_l gnd vdd vdd vdd vddq vddq vddq vddq vddq gnd gnd vddq vddq vddq vddq vdd vdd vdd vdd gnd data4 6 data4 8 data5 0] 4 5 cpid4 ifc_cf g0 iwidth vdd vdd data4 9 data5 1 data5 8 5 6 ifc_cf g2 cpid5 cpid3 vdd vdd data5 2 data5 4 data5 6 6 7 tck tdi ifc_cf g1 vdd vdd data5 5 data5 7 data5 9 7 8 cpid7 cpid6 tms vddq vddq data5 8 data6 0 data6 1 8 9 desc_ afull cam_f ull trst_l vddq vddq data6 2 data6 3 intr 9 10 tdo clk2x phs_l vddq vddq scane scan m testm 10 11 cmd1 cmd0 orst_ l vddq vdd vdd gnd gnd vdd vdd vddq xver_ 2 xver_ 1_l xver_ 1 11 12 cmd4 cmd3 cmd2 vddq vdd gnd gnd gnd gnd vdd vddq dq_72 sclk soe_l 12 13 cmd7 cmd6 cmd5 gnd gnd gnd gnd gnd gnd gnd gnd sdata 63 sdata 62 sdata 61 13 14 cmd8 cmdv dq0 gnd gnd gnd gnd gnd gnd gnd gnd sdata 58 sdata 59 sdata 60 14 15 dq1 dq2 dq3 vddq vdd gnd gnd gnd gnd vdd vddq sdata 55 sdata 56 sdata 57 15 16 dq4 dq5 dq6 vddq vdd vdd gnd gnd vdd vdd vddq sdata 52 sdata 53 sdata 54 16 17 dq7 dq8 dq9 vddq vddq sdata 49 sdata 50 sdata 51 17 18 dq10 dq11 dq12 vddq vddq sdata 45 sdata 47 sdata 48 18 19 dq13 dq14 dq16 vddq vddq sdata 42 sdata 44 sdata 46 19 20 dq15 dq17 dq19 vdd vdd sdata 39 sdata 41 sdata 43 20 21 dq18 dq20 dq22 vdd vdd sdata 36 sdata 38 sdata 40 21 22 dq21 dq23 dq25 vdd vdd sdata 33 sdata 35 sdata 37 22 23 dq24 xver_0 dq26 gnd vdd vdd vdd vddq vddq vddq vddq vddq gnd gnd vddq vddq vddq vddq vdd vdd vdd vdd gnd sdata 28 sdata 32 sdata 34 23 24 xver_0 _l dq27 dq29 dq32 dq37 full dq42 ssv dq47 dq50 dq53 dq55 dq58 dq61 dq65 sdata 0 sdata 3 sdata6 sdata 10 sdata 13 sdata 16 sdata 19 sdata 22 sdata 25 sdata 29 sdata 31 24 25 dq28 dq30 dq33 dq36 dq39 dq41 dq44 dq46 dq49 dq51 dq54 dq56 dq59 dq62 dq64 dq67 sdata 2 sdata5 sdata8 sdata 11 sdata 14 sdata 17 sdata 20 sdata 23 sdata 26 sdata 30 25 26 dq31 dq34 dq35 dq38 dq40 dq43 dq45 dq48 ssf dq52 eot dq57 ack dq60 dq63 dq66 sdata 1 sdata4 sdata7 sdata9 sdata 12 sdata 15 sdata 18 sdata 21 sdata 24 sdata 27 26 af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a
cyncp8019 2 document #: 38-02043 rev. *b page 34 of 42 table 16-6 contains an alphabetical listing of the pins marked out in figure 16-1 , above. table 16-6. cynpc80192 pinout description package ball number signal name signal type package ball number signal name signal type a1 data[43] i/o ab1 data[12] i/o a10 testm input ab2 data[10] i/o a11 xver_1 output ab23 v dd 2.5 volts a12 soe_l input ab24 dq[37] i/o a13 sdata[61] i/o ab25 dq[39] i/o a14 sdata[60] i/o ab26 dq[40] i/o a15 sdata[57] i/o ab3 data[08] i/o a16 sdata[54] i/o ab4 v dd 2.5 volts a17 sdata[51] i/o ac1 data[09] i/o a18 sdata[48] i/o ac10 v ddq 3.3 volts a19 sdata[46] i/o ac11 v ddq 3.3 volts a2 data[44] i/o ac12 v ddq 3.3 volts a20 sdata[43] i/o ac13 v ss ground a21 sdata[40] i/o ac14 v ss ground a22 sdata[37] i/o ac15 v ddq 3.3 volts a23 sdata[34] i/o ac16 v ddq 3.3 volts a24 sdata[31] i/o ac17 v ddq 3.3 volts a25 sdata[30] i/o ac18 v ddq 3.3 volts a26 sdata[27] i/o ac19 v ddq 3.3 volts a3 data[47] i/o ac2 data[07] i/o a4 data[50] i/o ac20 v dd 2.5 volts a5 data[53] i/o ac21 v dd 2.5 volts a6 data[56] i/o ac22 v dd 2.5 volts a7 data[59] i/o ac23 v ss ground a8 data[61] i/o ac24 dq[32] i/o a9 intr output ac25 dq[36] i/o aa1 data[15] i/o ac26 dq[38] i/o aa2 data[13] i/o ac3 data[04] i/o aa23 v dd 2.5 volts ac4 v ss ground aa24 full input ac5 v dd 2.5 volts aa25 dq[41] i/o ac6 v dd 2.5 volts aa26 dq[43] i/o ac7 v dd 2.5 volts aa3 data[11] i/o ac8 v ddq 3.3 volts aa4 v dd 2.5 volts ac9 v ddq 3.3 volts ad1 data[06] i/o ae19 dq[14] i/o ad10 phs_l output ae2 data[01] i/o ad11 orst_l output ae20 dq[17] i/o ad12 cmd[2] output ae21 dq[20] i/o ad13 cmd[5] output ae22 dq[23] i/o ad14 dq[00] i/o ae23 xver_0 output ad15 dq[03] i/o ae24 dq[27] i/o ad16 dq[06] i/o ae25 dq[30] i/o
cyncp8019 2 document #: 38-02043 rev. *b page 35 of 42 ad17 dq[09] i/o ae26 dq[34] i/o ad18 dq[12] i/o ae3 cpid[0] output ad19 dq[16] i/o ae4 cpid[2] output ad2 data[03] i/o ae5 ifc_cfg[0] input ad20 dq[19] i/o ae6 cpid[5] output ad21 dq[22] i/o ae7 tdi input ad22 dq[25] i/o ae8 cpid[6] output ad23 dq[26] i/o ae9 cam_full output ad24 dq[29] i/o af1 data[02] i/o ad25 dq[33] i/o af10 tdo output ad26 dq[35] i/o af11 cmd[1] output ad3 data[00] i/o af12 cmd[4] output ad4 irst_l input af13 cmd[7] output ad5 iwidth input af14 cmd[8] output ad6 cpid[3] output af15 dq[01] i/o ad7 ifc_cfg[1] input af16 dq[4] i/o ad8 tms input af17 dq[07] i/o ad9 trst_l input af18 dq[10] i/o ae1 data[05] i/o af19 dq[13] i/o ae10 clk2x output af2 strb output ae11 cmd[0] output af20 dq[15] i/o ae12 cmd[3] output af21 dq[18] i/o ae13 cmd[6] output af22 dq[21] i/o ae14 cmdv output af23 dq[24] i/o ae15 dq[02] i/o af24 xver_0_l output ae16 dq[05] i/o af25 dq[28] i/o ae17 dq[08] i/o af26 dq[31] i/o ae18 dq[11] i/o af3 cpid[1] output af4 big_ltl_l input c13 sdata[63] i/o af5 cpid[4] output c14 sdata[58] i/o af6 ifc_cfg[2] input c15 sdata[55] i/o af7 tck input c16 sdata[52] i/o af8 cpid[7] output c17 sdata[49] i/o af9 desc_afull output c18 sdata[45] i/o b1 data[42] i/o c19 sdata[42] i/o b10 scanm input c2 data[41] i/o b11 xver_1_l output c20 sdata[39] i/o b12 sclk output c21 sdata[36] i/o b13 sdata[62] i/o c22 sdata[33] i/o b14 sdata[59] i/o c23 sdata[28] i/o b15 sdata[56] i/o c24 sdata[25] i/o b16 sdata[53] i/o c25 sdata[23] i/o b17 sdata[50] i/o c26 sdata[21] i/o table 16-6. cynpc80192 pinout description (continued) package ball number signal name signal type package ball number signal name signal type
cyncp8019 2 document #: 38-02043 rev. *b page 36 of 42 b18 sdata[47] i/o c3 v ss ground b19 sdata[44] i/o c4 data[46] i/o b2 v ss ground c5 data[49] i/o b20 sdata[41] i/o c6 data[52] i/o b21 sdata[38] i/o c7 data[55] i/o b22 sdata[35] i/o c8 data[58] i/o b23 sdata[32] i/o c9 data[62] i/o b24 sdata[29] i/o d1 data[36] i/o b25 sdata[26] i/o d10 v ddq 3.3 volts b26 sdata[24] i/o d11 v ddq 3.3 volts b3 data[45] i/o d12 v ddq 3.3 volts b4 data[48] i/o d13 v ss ground b5 data[51] i/o d14 v ss ground b6 data[54] i/o d15 v ddq 3.3 volts b7 data[57] i/o d16 v ddq 3.3 volts b8 data[60] i/o d17 v ddq 3.3 volts b9 data[63] i/o d18 v ddq 3.3 volts c1 data[39] i/o d19 v ddq 3.3 volts c10 scane input d2 data[38] i/o c11 xver_2 output d20 v dd 2.5 volts c12 dq_72 i/o d21 v dd 2.5 volts d22 v dd 2.5 volts h1 rw_l input d23 v ss ground h2 oe_l input d24 sdata[22] i/o h23 v dd 2.5 volts d25 sdata[20] i/o h24 sdata[10] i/o d26 sdata[18] i/o h25 sdata[08] i/o d3 data[40] i/o h26 sdata[07] i/o d4 v ss ground h3 data[28] i/o d5 v dd 2.5 volts h4 v dd 2.5 volts d6 v dd 2.5 volts j1 ce2 input d7 v dd 2.5 volts j2 ce_l input d8 v ddq 3.3 volts j23 v ddq 3.3 volts d9 v ddq 3.3 volts j24 sdata[06] i/o e1 data[33] i/o j25 sdata[05] i/o e2 data[35] i/o j26 sdata[04] i/o e23 v dd 2.5 volts j3 ce2_l input e24 sdata[19] i/o j4 v ddq 3.3 volts e25 sdata[17] i/o k1 adr[7] input e26 sdata[15] i/o k2 adr[8] input e3 data[37] i/o k23 v ddq 3.3 volts e4 v dd 2.5 volts k24 sdata[03] i/o f1 data[30] i/o k25 sdata[02] i/o f2 data[32] i/o k26 sdata[01] i/o table 16-6. cynpc80192 pinout description (continued) package ball number signal name signal type package ball number signal name signal type
cyncp8019 2 document #: 38-02043 rev. *b page 37 of 42 f23 v dd 2.5 volts k3 adr[9] input f24 sdata[16] i/o k4 v ddq 3.3 volts f25 sdata[14] i/o l1 adr[4] input f26 sdata[12] i/o l11 v dd 2.5 volts f3 data[34] i/o l12 v dd 2.5 volts f4 v dd 2.5 volts l13 v ss ground g1 bwe_l input l14 v ss ground g2 data[29] i/o l15 v dd 2.5 volts g23 v dd 2.5 volts l16 v dd 2.5 volts g24 sdata[13] i/o l2 adr[5] input g25 sdata[11] i/o l23 v ddq 3.3 volts g26 sdata[09] i/o l24 sdata[00] i/o g3 data[31] i/o l25 dq[67] i/o g4 v dd 2.5 volts l26 dq[66] i/o l3 adr[6] input p16 v ss ground l4 v ddq 3.3 volts p2 clk input m1 adr[1] input p23 v ss ground m11 v dd 2.5 volts p24 dq[58] i/o m12 v ss ground p25 dq[59] i/o m13 v ss ground p26 ack input m14 v ss ground p3 xver_2_l output m15 v ss ground p4 v ss ground m16 v dd 2.5 volts r1 bw_l[3] input m2 adr[2] input r11 v dd 2.5 volts m23 v ddq 3.3 volts r12 v ss ground m24 dq[65] i/o r13 v ss ground m25 dq[64] i/o r14 v ss ground m26 dq[63] i/o r15 v ss ground m3 adr[3] input r16 v dd 2.5 volts m4 v ddq 3.3 volts r2 bw_l[4] input n1 bw_l[1] input r23 v ddq 3.3 volts n11 v ss ground r24 dq[55] i/o n12 v ss ground r25 dq[56] i/o n13 v ss ground r26 dq[57] i/o n14 v ss ground r3 bw_l[5] input n15 v ss ground r4 v ddq 3.3 volts n16 v ss ground t1 bw_l[6] input n2 bw_l[0] input t11 v dd 2.5 volts n23 v ss ground t12 v dd 2.5 volts n24 dq[61] i/o t13 v ss ground n25 dq[62] i/o t14 v ss ground n26 dq[60] i/o t15 v dd 2.5 volts n3 adr[0] input t16 v dd 2.5 volts table 16-6. cynpc80192 pinout description (continued) package ball number signal name signal type package ball number signal name signal type
cyncp8019 2 document #: 38-02043 rev. *b page 38 of 42 n4 v ss ground t2 bw_l[7] input p1 bw_l[2] input t23 v ddq 3.3 volts p11 v ss ground t24 dq[53] i/o p12 v ss ground t25 dq[54] i/o p13 v ss ground t26 eot input p14 v ss ground t3 data[27] i/o p15 v ss ground t4 v ddq 3.3 volts u1 data[26] i/o w1 data[21] i/o u2 data[25] i/o w2 data[19] i/o u23 v ddq 3.3 volts w23 v ddq 3.3 volts u24 dq[50] i/o w24 ssv input u25 dq[51] i/o w25 dq[46] i/o u26 dq[52] i/o w26 dq[48] i/o u3 data[24] i/o w3 data[17] i/o u4 v ddq 3.3 volts w4 v ddq 3.3 volts v1 data[23] i/o y1 data[18] i/o v2 data[22] i/o y2 data[16] i/o v23 v ddq 3.3 volts y23 v dd 2.5 volts v24 dq[47] i/o y24 dq[42] i/o v25 dq[49] i/o y25 dq[44] i/o v26 ssf input y26 dq[45] i/o v3 data[20] i/o y3 data[14] i/o v4 v ddq 3.3 volts y4 v dd 2.5 volts table 16-6. cynpc80192 pinout description (continued) package ball number signal name signal type package ball number signal name signal type
cyncp8019 2 document #: 38-02043 rev. *b page 39 of 42 17.0 ordering information table 17-1 provides ordering information for the cyncp80192 device. table 17-1. ordering information part number description frequency temperature range cynpc80192-bgc network database coprocessor 100 mhz commercial
cyncp8019 2 document #: 38-02043 rev. *b page 40 of 42 18.0 package drawings in the following figures the ndc package diagrams are shown from various views. figure 18-1 shows the package from a bottom view, figure 18-2 from a side view, and figure 18-3 from a top view. figure 18-1. package bottom view figure 18-2. package side view
cyncp8019 2 document #: 38-02043 rev. *b page 41 of 42 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. zbt is a trademark of integrated device technology. syncburst is a trademark of micron technology. all product and company names mentioned in this document are the trademarks of their respective holders. figure 18-3. package top view
cyncp8019 2 document #: 38-02043 rev. *b page 42 of 42 document history page document title: cyncp80192 network database coprocessor document number: 38-02043 rev. ecn no. issue date orig. of change description of change ** 111444 01/29/02 afx new data sheet *a 115873 05/17/02 fsg typo in ordering information table (changed from cyncp80192-100 to CYNCP80192-BGC) *b 127446 08/29/03 dcu clarified scope and description of big/ltl_l signal clarified ssram feature support corrected timing diagram for syncbu rst ssram interface (early write)

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